A Tale of Two Alphas

A Tale of Two Alphas

DEC's new Alpha RISC chip provides high-end performance for both a Unix workstation and a Windows NT server

By RICK GREHAN

BYTE Magazine

DECEMBER 1993

Promising to bring to the desktop a level of computing power once available only from supercomputers, DEC's new Alpha AXP microprocessor recently arrived in two very different guises. The DEC 3000 Model 300 is a small but powerful Unix box with DEC's TurboChannel expansion bus; the DECpc AXP 150 is a compact EISA server that runs Microsoft Windows NT.

Lack of applications makes it hard to flesh out the full performance picture for these two Alpha systems, but a detailed under-the-hood examination and testing with BYTE' s low-level benchmarks gets the process off to a good start. Both systems use a 150-MHz version of DEC's 21064 Alpha CPU, a 64-bit RISC chip.

The architectures of these two machines are quite different, however, with some resulting performance implications. The Model 300 channels data to its CPU via a 64-bit data bus. The AXP 150 provides the Alpha chip with a 128-bit external data bus and a 512-KB secondary RAM cache

that is twice the size of the Model 300's.

Although the two systems are aimed at different markets, the AXP 150 generally does a better job of getting the most power from its Alpha chip.

DEC 3000 Model 300

The Model 300 is the low end of a line of Alpha-based systems designed to run DEC OSF/1, a Unix operating system that supports the DECwindows GUI. DECwindows is more or less a variant of the X Window System. The Model 300's steep entry-level price of $9995 includes a 16-inch color monitor, 32 MB of RAM. a 426-MB SCSI hard drive, and built-in 1280-by 1024-pixel, 256-color accelerated graphics. DEC also provides OSF/1 and all necessary licenses.

Besides the model I reviewed, the DEC 3000 series includes the Model 500. Model 400, and several variants. Models differ in their initial hardware and ultimate expandability. For example, the Model 500 is capable of handling up to 1 GB of system memory, while the Model 300 tops out at just 256 MB. The Model 300 uses parity checking, while the 400 and 500 use ECC (error-correction code).

Compared to the 400 and 500, the Model 300's design sacrifices performance for the sake of cost. Its 64-bit external data bus and 256-KB external cache are half-size compared to those of the higher models. The even less expensive Model 300L forgoes Turbo-Channel expansion slots and runs its Alpha chip at 100 MHz instead of 150 MHz.

DEC provides several graphics configurations for the 3000 line; again. the exact configuration depends primarily on the particular model. The Model 300 system I tested came with a 16-inch color monitor driven by DEC's own HX graphics accelerator. This on-board accelerator provides eight planes of color (256 simultaneous colors on-screen), a frame buffer, and a graphics coprocessing system that' off-loads from the main CPU such fundamental 2-D operations as drawing lines and rectangles. Resolution is 1280 by 1024, pixels with a 72-Hz refresh rate.

The Model 300's 150-MHz Alpha microprocessor communicates to the rest of the system through separate address and data buses (see the figure "DEC 3000 Model 300 Bus Architecture"). The 34-bit address bus contains a separate cache-tag address bus that feeds the cache circuitry; it provides the mechanism to associate memory blocks in the cache with physical memory in system DRAM.

The Model 300's external 256-KB cache is direct-mapped and write-back. The cache's write-back nature means that a write operation from the CPU does not necessarily trigger a write to the slower system memory. Data moves from the SRAM cache to the slower DRAM main memory only when absolutely necessary. This cache augments the Alpha chip's own internal 8-KB instruction and 8-KB data caches (the internal data cache is a write-through cache). For increased performance, the address-data-control logic allows concurrent traffic between the TurboChannel bus and system DRAM and between the CPU and its memory cache.